Application Design of Motor Serial Communication Based on EPM570T144C5 and Absolute Encoder

At present, the servo motors in domestic CNC machine tools are generally equipped with incremental encoders, but the accuracy of incremental encoders is not very high and the output is parallel signals. To improve its accuracy, it is necessary to increase the design of the encoder. It is difficult and increases the output of parallel signals, which is not conducive to the long-distance communication between the servo unit and the encoder.

Author: Liao Wengao

introduction

At present, the servo motors in domestic CNC machine tools are generally equipped with incremental encoders, but the accuracy of incremental encoders is not very high and the output is parallel signals. To improve its accuracy, it is necessary to increase the design of the encoder. It is difficult and increases the output of parallel signals, which is not conducive to the long-distance communication between the servo unit and the encoder. The absolute encoder, in addition to its accuracy several times higher than the incremental encoder, the input and output of its signals are all using high-speed serial communication, saving communication lines for long-distance communication. At the other end of the encoder, CPLD is used for high-speed serial communication with the absolute encoder. The CPLD then converts the received encoder information into parallel data and transfers it to the DSP in the servo unit for operation control. This text will give the software and hardware design scheme of high-speed serial communication between CPLD and absolute encoder.

hardware design

The hardware is mainly composed of three modules: power supply, CPLD and its peripheral circuits and absolute encoder interface circuit.

power module

Application Design of Motor Serial Communication Based on EPM570T144C5 and Absolute Encoder
Figure 1 Block diagram of power supply structure

The switching power supply in the figure converts the 220V AC grid voltage into +5V, +15V, -15V. The switching power supply can filter out various interferences in the power grid, and the transformer in the switching power supply connects 220VAC with the output +5V, +15V , -15V isolation, the internal circuit also uses TL431 to adjust the conduction pulse width of the switching tube, so the anti-interference, safety, stability and voltage regulation of the switching power supply are better.

TPS7333 is a DC/DC chip, which converts +5V DC voltage into +3.3V stable DC voltage for CPLD use. TPS7333 has better conversion efficiency, reliability and voltage stability. It has an input voltage of +3.77V~+ It can convert +3.3V within the voltage range of 10V, so that the CPLD will not be burned out due to excessive input voltage.

CPLD and its peripheral circuit modules

CPLD and its peripheral circuit modules are mainly composed of CPLD, CPLD programming download interface circuit (JTAG interface), DSP interface circuit, active crystal oscillator, level conversion circuit, ADM485 and its peripheral circuit (interface circuit responsible for communication with the encoder) ( figure 2).

Application Design of Motor Serial Communication Based on EPM570T144C5 and Absolute Encoder
Figure 2 Block diagram of the overall hardware structure

The JTAG interface is mainly used to download executable files to the CPLD, install Altera’s development environment – QUARTUS II on the PC, and compile the written VHDL program in this development environment to ensure that the compilation is error-free and that the function has been implemented. , connect the download cable to the JTAG interface, and download the CPLD circuit board through the programming download tool provided by QUARTUS II.

The DSP interface is composed of 8 data lines, 3 address lines and 1 control line. The 8 data lines are responsible for transmitting encoder data and other information, and the 3 address lines are responsible for transmitting DSP commands and decoding at the CPLD terminal. , CPLD transmits encoder data or other information to DSP through 8 data lines according to the command obtained by decoding, and the control line is mainly to complete the synchronous control of CPLD and DSP.

The 20M active crystal oscillator mainly provides the reference clock for the CPLD. Driven by the clock signal, the CPLD generates a baud rate of 2.5Mb/s to communicate with the encoder, and generates a 10MHz clock for some logic control signals. This crystal oscillator provides The clock frequency of 20MHz requires a DC voltage of 3.3V from the power supply.

The level conversion circuit is mainly responsible for converting the 3.3V voltage to 5V or converting the 5V voltage to 3.3V, because the power supply voltage required by the core and I/O ports of the CPLD is 3.3V, while the ADM485 and the absolute encoder need The power supply voltage and I/O port drive voltage are both 5V, so it is necessary to use the level conversion chip LVC4245A to convert 3.3V to 5V or convert 5V to 3.3V.

ADM485 and its peripheral circuits are the hardware connection of high-speed communication between CPLD and absolute encoder. The working voltage of ADM485 is 5V, and its maximum communication rate is 5Mb/s. Using two ADM485 chips for docking communication can improve the anti-interference ability on the communication line, and the longest transmission distance can reach 1.2km. Its peripheral circuit is shown in Figure 3. The right half of the dotted line belongs to the external circuit of the absolute encoder. The pull-up and pull-down resistors are both 1K ohms, and the current limiting resistor is 220Ω. SDAT of ADM485 is the data output pin, ADM485 SRQ is the data input pin, DE of ADM485 is the external control pin, this pin is controlled by CPLD, because the RS-485 communication protocol is half-duplex, so ADM485 can only be in the state of sending data or receiving data, when ADM485 When the DE of ADM485 is high, the ADM485 is in the data output state (that is, the CPLD receives data). When the DE of the ADM485 is low, the ADM485 is in the data input state (that is, the CPLD sends data).

Application Design of Motor Serial Communication Based on EPM570T144C5 and Absolute Encoder
Figure 3 Absolute encoder interface circuit

Absolute encoder interface module

The absolute encoder interface module refers to the power supply and signal input and output interface circuit inside the absolute encoder. Its circuit is consistent with the above-mentioned ADM485 and its peripheral circuits. It also uses the ADM485 chip and some pull-up, pull-down and current limiting. resistance. As shown in Figure 3, the left half of the dotted line is the internal interface circuit of the absolute encoder, which is responsible for connecting with the external ADM485 (the right half of the dotted line). ADM485 is controlled by the control chip inside the encoder. When the encoder receives After the command sent by the CPLD, the control chip makes a judgment and sends the corresponding data, and at the same time controls the DE of the ADM485 to a high level, even if the ADM485 is in the sending state, after the data is sent, the control chip makes the DE of the ADM485 low. The level state is convenient to receive commands from the CPLD at any time.

software design

Software refers to the VHDL program of CPLD, which is mainly composed of six software sub-modules: frequency divider, receiving DSP control commands, CPLD logic control, baud rate generator, receiving and sending data, serial-to-parallel conversion and sending data (Figure 4). ).

Application Design of Motor Serial Communication Based on EPM570T144C5 and Absolute Encoder
Figure 4 Block diagram of the overall structure of the software

divider module

The frequency divider module mainly divides the 20MHz input clock frequency into 10MHz and 2.5MHz clock frequencies, of which the 10MHz clock is mainly for the CPLD logic control module, and the 2.5MHz clock is mainly for the baud rate generator module.

Receive DSP control command module

The module that receives the DSP control command actually collects the control signal sent by the DSP in real time and decodes the control signal in time. After the decoding is completed, it is immediately transferred to the CPLD logic control module.

CPLD logic control module

The CPLD logic control module is the core of the entire CPLD software. After it receives the decoded data, it immediately performs logic control operations, and quickly controls the receiving and sending data modules and the control serial-to-parallel conversion and sending data modules.

Baud Rate Generator Module

The baud rate generator module mainly provides 2.5Mb/s baud rate for receiving and sending data modules.

Receive and send data module

The receiving and sending data module is an important part of the entire CPLD software. It is mainly responsible for high-speed communication with the absolute encoder. Since its communication mode is asynchronous serial communication, its baud rate, communication data format and RS-485 The communication protocol must be the same as the absolute encoder.

Serial-to-parallel conversion and sending data module

The serial-to-parallel conversion and transmission data module mainly converts the received encoder serial data into parallel data, and locks the data in the CPLD latch. When the CPLD logic control module controls the transmission data, it will be latched in the CPLD. The data in the latch is sent to the DSP in a parallel manner for the DSP to perform arithmetic control.

Epilogue

This design has completed all the hardware and software design. It only takes 31mS to read any position data of the motor rotor with an absolute encoder, and the communication rate can reach 2.5Mb/s. Integrating this design into the servo drive unit, the rotational speed of the motor can be driven and controlled up to 6000 rpm, and the positional accuracy of the control motor rotor can be up to mM.

The Links:   LB121S03-TL02 2MBI150NC-060