Design of Data Acquisition System Based on TMS320VC540 and CY7C026 Chips

The front-end data acquisition system controlled by the industrial computer through the PCI bus has been widely used in the field of industrial control. The general data transmission system will cause data congestion in the case of large data volume. In the process of system design, after many comparisons, the high-speed data exchange interface composed of high-number dual-port RAM has successfully solved this problem.

Author: Fan Fan, Kuo Yonghong

The front-end data acquisition system controlled by the industrial computer through the PCI bus has been widely used in the field of industrial control. The general data transmission system will cause data congestion in the case of large data volume. In the process of system design, after many comparisons, the high-speed data exchange interface composed of high-number dual-port RAM has successfully solved this problem.

CY7C026 is a 16K×16 high-speed dual-port static RAM produced by CYPRESS, and its access speed is less than 25ns. It has a true dual port, which can simultaneously access data. The two ports have independent control signal lines, address lines and data lines. In addition, the storage capacity and data width can be easily expanded through the master/slave selection. Through the chip’s semaphore marker, the left and right ports can realize the sharing of chip resources. The internal functional block diagram of the CY7C026 chip is shown in Figure 1.

Design of Data Acquisition System Based on TMS320VC540 and CY7C026 Chips
Figure 1 Internal functional block diagram of CY7C026 chip

How CY7C026 Works

Access principle

It can be seen from the internal structure diagram of CY7C026 that the core part of the chip is a dual-port storage array. The left and right ports can share the storage array and have their own control lines. When accessing data separately, it is the same as ordinary RAM. . When reading data in different storage spaces at the same time and reading data in the same data space at the same time, the left and right ports can be performed at the same time. If a write operation is performed to the same data space at the same time, or a port performs a read operation to a data space while another port performs a write operation to the data space, the left and right ports will conflict. To this end, the CY7C026 handles both cases through the BUSY pin.

When the left and right ports perform read and write operations on different storage spaces, they can be accessed at the same time. At this time, the BUSY signals of the left and right ports are set high at the same time. If the same storage space is stored at the same time, which end of the storage request signal appears first, then the end of the BUSY signal is set high, allowing storage. Which end of the storage signal appears later, then the BUSY signal of this end is set low, and the storage is prohibited.

It is worth noting that the time difference between the access request signals at the left and right ends must be greater than 5ns, otherwise the arbitration logic cannot determine which side of the access request signal appears first. If the time difference between the access request signals at both ends is less than 5ns, the arbitration logic will set the BUSY signal on one side to high and the BUSY signal on the other side to low, thus ensuring that one of the two ports executes data storage and the other port executes data storage. read, avoiding conflicts.

Interrupt function and use of master/slave mode

The interrupt function of CY7C026 chip is realized by “mailbox”. The so-called “letter box” means that the chip uses the high address 3FFF of the memory as the “letter box” of the left port, and 3FFE as the “letter box” of the right port. The following takes the left port to transmit data to the right port as an example to illustrate the usage of the interrupt function. When the left port writes data to the “mailbox” of the right port, the INTR pin of the right port will generate an interrupt signal, that is, the INTR pin is set low. After the right port reads the data, the interrupt signal is automatically reset. The case where the right port transfers data to the left port is the same as above. Users need to be clear that this function is only suitable for low-speed transmission of data.

In practice, the width of the data is often greater than 16 bits. At this time, it is necessary to expand the width of the data bit. The M/S pin of CY7C026 provides the function of data expansion. For example, a 32-bit data bus is often required in practical applications. You can set the M/S pin of one CY7C026 to low and the M/S pin of the other to high, and then connect the pins of the two chips together. .

Design of Data Acquisition System Based on TMS320VC540 and CY7C026 Chips
Figure 2 Block diagram of high-speed data acquisition and transmission system

Use of semaphore flags

Application of CY7C026 in Data Transmission System

The designed system is a subsystem of petroleum logging equipment. The system uses TMS320C5402 as the main processor and uses dual-port RAM CY7C026 as the data sharing interface. Its main function is to receive the command written to the dual-port RAM by the industrial computer through the CPCI interface, and the DSP sends the command to the downhole instrument. After the corresponding downhole instrument receives the command, it collects the downhole data, and then transmits the data to the DSP. The data processed by DSP is written into dual-port RAM. Finally, the industrial computer transmits the data in the dual-port RAM to the computer for Display processing through the CPCI interface. The system block diagram is shown in Figure 2.

concluding remarks

Using the high-speed data transmission capability of dual-port RAM CY7C026 and the high-speed performance of DSP TMS320VC5402 can meet the requirements of high-speed data transmission, and can complete a large number of complex data processing tasks, thus taking into account the high throughput and high speed required for data transmission processing.

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