How to get the high-speed serial bus? Where is the difficulty?

Differential wiring, number of vias for signal layer change, equal length control, impedance control requirements, loss across divisions, position and shape of the corners of the wiring, insertion loss and return loss corresponding to the winding method, one caused by improper layout Serial crosstalk and stacked crosstalk, improper layout to operate the stub that exists on the pad.

The development of serial bus can be summarized into three phases at present:

Clock parallel bus: less than 200MHZ, such as CPCI, PCIX, SDRAM, ISA, PIC

Source synchronous clock parallel bus: less than 3200Mbps, such as DDRr1234 series, MII, EMMC

High-speed serial bus: up to 56NRZ, such as USB1/2/3/3.1/3.2, PCIE3, PCIE4, SAS3, SAS4

Then we pay attention to the following points in the design process for the processing of important line signals of these signals:

Differential wiring, number of vias for signal layer change, equal length control, impedance control requirements, loss across divisions, position and shape of the corners of the wiring, insertion loss and return loss corresponding to the winding method, one caused by improper layout Serial crosstalk and stacked crosstalk, improper layout to operate the stub that exists on the pad.

1. Differential wiring, the differential wiring strictly follows the conclusions drawn from the differential simulation, 2S, and 3W requirements for control wiring, the purpose of which is to enhance the coupling performance of signal quality and reduce signal return loss.

How to get the high-speed serial bus? Where is the difficulty?

How to get the high-speed serial bus? Where is the difficulty?

2. The number of vias in the signal layer is a fatal injury to important signal lines, especially for signal lines with high-speed signal frequencies. Once the number of vias is too large, return loss will increase. So punching is not just punching when you encounter a line, especially our clock line.

How to get the high-speed serial bus? Where is the difficulty?

3. Equal length control

How to get the high-speed serial bus? Where is the difficulty?

According to the equal length requirements of the corresponding devices, the line segments of the data are matched with the same length, so as to ensure the stability of data transmission and the synchronization of the data file transmission sequence.

4. Loss across divisions. Important line segments cannot be routed across divisions to avoid return loss and insertion loss in our signal.

How to get the high-speed serial bus? Where is the difficulty?

5. Try to avoid the stub layout in the layout of the signal line, as shown in the figure.

How to get the high-speed serial bus? Where is the difficulty?

6. Which is better, right angle, chamfer, or arc?

Through simulation, in fact, arc routing is the best. The signal has no reflect reflection, and there will be more or less chamfers, but the reflection does not come from a right angle. When our device A is transmitted to device B, there will naturally be a signal. There is reflection back to our device A during the transmission. When our device B transmits to device A, the signal will return to our device B because of the reflection at right angles.

How to get the high-speed serial bus? Where is the difficulty?

How to get the high-speed serial bus? Where is the difficulty?

The Links:   7MBI100U4S-120 LM64P101R IGBT