How to protect your analog front end when the performance of electronic components declines?

EOS is a general term that means that the system is under excessive pressure because too many electrons try to enter the circuit through the corresponding path. One thing to note is that this is a function of power and time.

How to protect your analog front end when the performance of electronic components declines?

What is EOS?

EOS is a general term that means that the system is under excessive pressure because too many electrons try to enter the circuit through the corresponding path. One thing to note is that this is a function of power and time.

If you think of a complex circuit as a simple power-consuming component, for example, think of it as a resistor. Applying a voltage of 1.1 V to a 1 Ω resistor with a rated power of 1 W, the formula for calculating power consumption is as follows:

How to protect your analog front end when the performance of electronic components declines?

It is calculated that the power consumption is 1.21 W. Although the rated power of the resistor is 1 W, there may be some margin, so don’t worry about this for now. But this is not always the case.

What happens when the voltage is increased to 2 V? If the power consumption reaches 4 times of the previous example, then the resistance may increase the ambient temperature in a very limited time like a space heater, but please remember this formula:

How to protect your analog front end when the performance of electronic components declines?

What if you increase the voltage to 10 V, but only last for 10 milliseconds? The interesting part is here: if you don’t understand the part and the purpose of designing and processing the part, you can’t really understand what impact it will have. Now, let’s take a look at the entire component system.

Which parts are susceptible to EOS?

Generally speaking, any part that contains Electronic components is easily affected by EOS. Particularly weak parts are those interfaces with the outside world, because they are likely to be the first parts that come into contact with electrostatic discharge (ESD), lightning strikes, etc. The parts we are interested in include the USB port, the analog front end of the oscilloscope, and the charging port of the latest high-performance IoT mixer.

How to protect your analog front end when the performance of electronic components declines?

Figure 1. Ideal contact discharge current waveform at 8 kV.

How do I know which problems to prevent?

Although we want to protect the system from electrical overload, the term is too broad and does not help in deciding how to protect the system. For this reason, the IEC (and many other organizations) have done a lot of work to figure out the types of EOS that may be encountered in real life. Then I will focus on the IEC specifications, because they cover a wide range of market applications, and the confusion related to the specifications also shows that this article is needed to clarify. Table 1 shows three specifications that define the types of EOS conditions that the system may encounter. In this article, only ESD will be discussed in depth, and it will also familiarize everyone with electrical fast transients (EFT) and surges.

How to protect your analog front end when the performance of electronic components declines?

Figure 2. Electrical fast transient level 4 waveform conforming to IEC61000-4-4 standard.

How to protect your analog front end when the performance of electronic components declines?

Table 1. IEC specifications

How do IC manufacturers deal with chip ESD?

The protection in the chip is mainly used to deal with the ESD in the manufacturing process, rather than the ESD in the power-on state of the system. This difference is very important, because when the amplifier is connected to a power source and not connected to a power source, its response to static electricity is very different. For example, internal protection diodes can eliminate the impact of electrostatic discharge on components when there is no power supply. However, when there is a power supply, the impact of electrostatic discharge on the component may cause the current conducted by the internal structure to exceed the designed tolerable level, which may cause the component to be damaged, depending on the component and the power supply voltage.

This is a problem that needs to be solved on a global scale! How to protect IC from this potential threat?

I hope you can realize that this challenge involves many factors, and a simple solution cannot be applied to all situations. Below is a list of factors involved, listing the factors that determine whether a component can withstand an EOS event. These factors are divided into two groups: uncontrollable factors and controllable factors.

Uncontrollable factors:

・IEC Waveform: The curves of ESD, EFT and surge are different, and they will attack certain weaknesses of the device in different ways.

· Consider the process technology of the device: Some process technologies are more prone to latch-up than others. For example, the CMOS process is prone to latch-up, but in many modern processes, this hazard can be mitigated by careful design and trench isolation.

• Consider the internal structure of the device: There are many design methods for integrated circuits, so an effective protection scheme for one circuit may not be effective for another. For example, many devices have sequential circuits, and the protection structure is activated when the waveform is detected to be fast enough. This may mean that if you add more capacitance to the location of the electrostatic discharge, the device that can withstand the impact of the electrostatic discharge may not be able to withstand the impact of this capacitance. This result is unexpected, but it is very important to recognize the following: The common circuit protection method, the RC filter, may make the situation worse.

How to protect your analog front end when the performance of electronic components declines?

Figure 3. The IEC61000-4-5 surge turns into a normal state at the 8 μs/20 μs current waveform position.

Factors that can be controlled:

・PCB layout: The closer the component is to the impact location, the higher its electrical energy waveform. This is because when the impulse waveform propagates along a certain path, the electromagnetic waves radiated from the propagation path will have energy loss, which is caused by the heat generated by the path resistance and the parasitic capacitance and inductance coupled with the surrounding conductors.

・Protection circuit: This is the most meaningful part for the survivability of the device. The above-mentioned uncontrollable factors will affect the design of the protection scheme.

・ Now there are over-voltage protection (OVP) and over-limit (OTT) features. Can these characteristics be used to protect the circuit from high-voltage transients?

The OVP and OTT characteristics allow the input of the component to withstand a voltage exceeding the power supply voltage without itself being damaged. Relying on these characteristics to protect the circuit from high-voltage transients is like relying on rain boots to deal with high-pressure flushers. Rain boots are only effective for shallow water where the water depth does not exceed its height, just like OVP and OTT are only suitable for voltages lower than their rated value. The rated voltage of OVP and OTT is tens of volts higher than the given power rail voltage. It cannot withstand the high voltage of 8000V.

How to know whether the protection circuit is effective?

By combining device knowledge, experience, and testing, you can roughly know which components should be used in the system to be the most beneficial. In order to ensure that the device is controllable, various manufacturers provide a wide range of protection components. This article only discusses two circuit protection schemes that have been proven to effectively protect the analog front end. The following scheme assumes a buffered operational amplifier. This is considered the most rigorous protection test, because the non-inverting input will withstand all shocks, other than that, the electrical energy has nowhere to go (before the protection circuit is installed).

How to protect your analog front end when the performance of electronic components declines?

Figure 4. The circuit used in the IEC-61000-4-2 test.

Design considerations:

・ R1 should be an anti-pulse (thick film) resistor so that it will not be easily destroyed when subjected to high voltage transients.

・ R1 voltage noise is proportional to the square root of the resistance value. This is an important consideration if the system requires low noise.

・ C1 should be a ceramic capacitor with a package size of at least 0805 to reduce the surface arc of the package.

・ C1 should be at least X5R type temperature coefficient capacitor (ideally C0G/NP0 type) to maintain a predictable capacitance value.

・ The equivalent series inductance and resistance inside C1 should be as low as possible to effectively absorb shocks.

・ For a given package size, the rated voltage of C1 should be as high as possible (minimum 100 V).

・ In this example, the position of C1 is before R1 because it constructs a capacitive voltage divider in which a 150 pF capacitor (as shown in Figure 5) discharges the ESD waveform into the system, so that the energy before the amplifier experiences the waveform Already diverted first.

How to protect your analog front end when the performance of electronic components declines?

Figure 5. Input protection is achieved by configuring a low-pass filter on the analog input terminal.

How to protect your analog front end when the performance of electronic components declines?

RC network protection scheme

RC network protection scheme

Note: Although this front-end protection method has not been approved by capacitor manufacturers, it has proven effective in hundreds of tests on amplifiers. The ESD test curve (described below) has only been tested on a limited range of capacitor products. Therefore, if you use different capacitor products, you need to first characterize their impact resistance characteristics, such as measuring the capacitance and The method of equivalent series resistance is very important. The capacitive device should maintain a stable capacitance value, and after being impacted, always maintain an open circuit state under DC.

Design considerations:

・Same as RC network: R1 should be able to withstand pulses, but noise may need to be considered.

・ The standards that D1 needs to meet should be specified. Some may only cover ESD, others cover EFT and surge standards.

・ D1 should be bidirectional, so that it can deal with both positive and negative shocks.

・ The reverse working voltage of D1 should be as high as possible while still passing the necessary tests. If it is too low, leakage current may occur under normal system voltage levels. If it is too high, you may not be able to react before the system is damaged.

The effect of TVS diode leakage on performance

In the field of analog electronics, everyone knows that TVS diodes are prone to leakage, so they cannot be used in precision analog front-ends.But sometimes this is not the case, the leakage current in many data sheets

How to protect your analog front end when the performance of electronic components declines?

Figure 6. Input protection is achieved by configuring TVS diodes on the analog input terminal.

How to protect your analog front end when the performance of electronic components declines?

TVS network protection scheme

If you choose the right TVS, the leakage current value may be so low that it surprises you. Figure 7 shows the leakage data obtained when measuring 12 TVS diodes of the same product model.

How to protect your analog front end when the performance of electronic components declines?

Figure 7. The leakage value of the 36 V bidirectional TVS diode Bournes T36SC, using the ADA4530 evaluation board in TIA, with shielding, and using a 10 G resistor at 25°C.

Among the 12 TVS diodes measured, when the DC bias voltage is 5 V, the most serious leakage is 7 pA. This is millions of times better than the value of the data table in the worst case. Of course, there are differences in leakage between different batches of TVS diodes, but this can at least explain the expected leakage amplitude. If the temperature experienced by the system does not exceed 85°C, TVS diodes may be a good choice. Just remember, if the product you choose is not the test product described in this article, please characterize its leakage characteristics. A conclusion that is correct for one component or manufacturer may not be correct for other components or manufacturers.

Test Results:

A series of operational amplifiers were tested using the IEC ESD standard. Table 2 shows the components suitable for protection by different protection schemes. Although the ESD standard stipulates that it is guaranteed to withstand three shocks at ±8 kV, all these solutions have passed the test of withstanding 100 shocks at ±9 kV to ensure that sufficient protection margin is provided.

How to protect your analog front end when the performance of electronic components declines?

How to protect your analog front end when the performance of electronic components declines?

Table 2. List of devices tested by IEC-61000-4-2 and their respective protection configurations

The EC standard requires that the ground terminal of the ESD source and the ground terminal of the amplifier are connected together by connecting two 470 kΩ resistors and a 30 pF capacitor in parallel. The setup of this test is more stringent. It directly connects the ground terminal of the ESD source with the ground terminal of the amplifier. These results have also been verified in the IEC ground coupling scheme, which can further enhance the reliability of the product. Please keep in mind that due to the large differences in the internal structure of the amplifier, the data applicable to the devices in this list may or may not be applicable to other devices. If other devices or other protective components are used, it is recommended to conduct a comprehensive test.

Protective components used:

・ Resistance: Panasonic 0805 ERJ-P6 series

・ Capacitance: Yageo 0805 100 V C0G/NPO

・ TVS diode: Bourns CDSOD323-T36SC (bidirectional, 36 V, very low leakage current, compliant with ESD, EFT and surge standards)

・ ESD varistor: Bourns MLA series, 0603 26 V

BBonus component: ESD varistor

TVS diodes have good performance and can withstand numerous shocks. This is very good for EFT and surge protection, but if you only need ESD protection, you might as well take a look at ESD varistors. Before reaching a certain voltage value, they are all used as high-voltage resistors. After reaching this voltage value, they change It is a low-voltage resistor, which can shunt the electric energy in the varistor.

The same configuration as the TVS diode can be used. They have less leakage and cost less than half of TVS diodes. Please note that its design does not require hundreds of shocks, and its resistance will drop with each shock. The ESD varistor has also been tested on the above products. When the series resistance value is about twice the value required by the TVS diode, the performance of the varistor is the best.

These products have only been tested under ESD standards. The unique feature of EFT is that although the voltage is not high (4 kV and below), its impact is explosive (5 kHz or above) and the rise time is slow (5 ns). The energy of each impact of the surge is about 1000 times that of EFT, but the speed is only 1/1000 of the waveform. If you need to cover these standards, please make sure to indicate on the data sheets of these protective components that they can deal with this problem.

Circuit protection overview

Although it seems that it is not difficult to add RC filters or TVS diodes to the circuit afterwards, please note that all other factors mentioned in this article will affect system performance and protection levels. This includes the layout, the components used in the front-end, and the IEC standards that need to be met. If you keep this in mind from the beginning, you can avoid emergencies that may require redesign in the final stages of system design.

This article is far from a comprehensive overview. The topic of sensitivity will be discussed in more depth in subsequent articles. In addition, other challenges in base station receiver design include automatic gain control (AGC) algorithms, channel estimation, and equalization algorithms. A series of technical articles will be launched in the follow-up, the purpose is to simplify the design process and improve everyone’s understanding of the receiver system.

The Links:   LM150X08-A4K8 KCS038AA1AJ-G21