In the golden age of the semiconductor industry, when Gordon Moore was still laying out the roadmap for his company, shrinking planar dimensions brought simultaneous advances in power, performance, and area/cost (PPAC). But over time, Dennard’s law of shrinking plane size was held back from helping power consumption, and materials engineering began to be applied to semiconductor manufacturing to facilitate continued improvements in power consumption, performance, and area/cost. Among them, the high-K value metal gate is a most powerful example.
Today, engineers generally acknowledge this paradox: Design engineers optimize for power consumption and performance, while process engineers engage in aggressive 2D scaling to reduce area and cost. Neither logic nor memory, especially as the industry’s production patterns shrink below 8nm, design advancements have not been organically combined with process innovation. While node naming sizes are shrinking, feature sizes are not shrinking as fast as they used to. In addition, we are also seeing a sharp slowdown in cost reductions (see Figure 1).
Figure 1: Complexity of chip design leads to slower feature size reduction and higher cost
Why isn’t size shrinking progressing as fast as it should? Why is high-end silicon still so expensive? The answer lies in the complexity of chip design – today’s chip design has many layers, and the layers must also be seamlessly connected.
Take DRAM as an example. A DRAM device has about seven key graphics layers, each of which is different (see Figure 2). In addition to the different physical structures of the shallow trench isolation (STI) layers, capacitors, bitlines, and wordlines, some layers have high aspect ratios, making it increasingly difficult to align the previous layer with the next. These various features must be well imaged and aligned to ensure proper device operation. However, the simultaneous shrinking of these distinct patterning layers brings greater complexity to the implementation of the process. Once the process does not meet the requirements, the pattern edge planarity error (EPE) increases resistance, degrades performance, and ultimately leads to yield loss and device failure.
Figure 2: Challenges to pattern shrinkage and alignment generated in DRAM’s respective different device layers
So, with the roadmap blocked, we need a “new strategy” to improve chip performance, power, area cost, and time-to-market (PPACt). The “new strategy” includes:
· New computing architecture
New on-chip devices and 3D structures
· A new approach to continuous 2D size reduction (topic of this blog)
Heterogeneous design and advanced packaging
From a device perspective, we need to do more than introduce new films or improve individual processes like etch. We also need to comprehensively consider and develop corresponding supporting technologies according to the needs of each device.
This evolution from a single process to a material-integrated solution can also help customers cut process steps, reduce R&D costs and time, and ultimately accelerate time-to-market. Here are three innovations I presented at the SPIE Advanced Lithography Conference earlier this year that demonstrate how chipmakers can benefit in multiple ways by using a holistic approach to advanced graphic imaging.
Right Angle Sidewall Mask Technology
The right-angle sidewall mask technology is an application of the self-aligned patterning twice (SADP) and the self-aligning patterning four times (SAQP). Sidewall deposition and sidewall etch are challenging in part because the materials used are relatively soft and prone to arcing at the top and bottom (not easy to form right angles). This leads to non-uniformity and pitch drift, which in turn contributes to lithography registration errors and vertical offset EPE – these kinds of fluctuation problems are exacerbated at smaller process nodes.
Chipmakers typically address fluctuations by adding additional process steps, which also add cost and complexity. In addition, while the additional hardmask etch and core mask etch processes reduce the volatility from the first sidewall etch, it also reduces the achievement of the critical dimension (CD) desired by the designer. In other words, the process steps to address EPE are accompanied by performance compromises that reduce the level of control over the design outcome.
A new process developed by Applied Materials optimizes the sidewall material to better accommodate the etch process, resulting in better alignment (see Figure 3). The process begins by depositing amorphous silicon with ALD-like precision using a CVD process, followed by pattern imaging with our Centris® Sym3® etch system, and measurement with a VeritySEM® system. We provide a solution that enables chipmakers to use traditional process steps while maintaining image fidelity, reducing the number of SAQP steps from 15 to 11 by removing unnecessary deposition and etch steps . Overall helps customers achieve graphic size reduction in a more cost-effective manner.
Figure 3: Applied’s unique sidewall material enables better uniformity and alignment compared to conventional processes
Lateral etching technology
Another unique technique developed by Applied Materials is called lateral etch. When using traditional photolithography and etching processes, designers can only combine features with limited tightness. This is called the minimum line spacing in the horizontal direction and the top-bottom thickness in the vertical direction. When using EUV, the minimum line spacing is currently about 36nm, and the top-bottom thickness is about 40nm. If these line spacings are too large for the design, chipmakers have to invest in additional patterning steps—either by adding mask cut-off or selective masking, or by adding EUV lithography-etch steps. The only alternative is to continue to use a larger die area, but this increases the die area/cost ratio.
Etching has traditionally been done top-down. But Applied Materials has developed an innovative lateral etch technique that enables etching at 45-degree angles, giving designers new degrees of freedom (see Figure 4). By controlling the etch direction, we can shrink the CD laterally while maintaining the vertical mask thickness. Facts have proved that we have been able to achieve a vertical film thickness of about 20nm under the independent shrinkage of lateral CD.
Figure 4: Applied’s innovative lateral etch technology reduces EUV mask count by 50% or more
Lateral etch allows designers to reduce process steps and combine features more tightly, thereby increasing areal density and benefiting more device applications. We co-optimize this process with our Producer® Precision® CVD carbon and silicon hardmasks, Sym3 etch, and PROVision® e-beam measurement and defect control to enable advanced graphics imaging solutions that give designers the opportunity to combine EUV mask count is reduced by 50% or more.
selective process technology
The third technology we are presenting at the SPIE Advanced Lithography Conference is a selective material deposition process. This process can solve the problem of EPE and improve the pattern reduction effect by controlling the dislocation between different device layers. Unlike traditional deposition, selective processing (deposition/etch) processes are used to eliminate EPE, resulting in reduced size and mask count on design rules.
For selective deposition to effectively reduce EPE, two key challenges must be overcome. First, the wafer surface must be clean enough to allow selective deposition on the desired material, but not others. Any defect on the wafer will compromise selectivity. The second challenge is to effectively control selectively deposited materials that grow not only vertically but also horizontally. Due to the above challenges, most selective depositions are limited to very thin layers.
Applied Materials has developed a co-optimized selective processing solution using the Endura deposition platform, Producer Selectra selective etch technology, and PROVision™ e-beam measurement and defect detection technology. We have demonstrated this process in the through-hole process flow shown in Figure 5. We start with the metal layer for selective material growth; then fill and planarize; then proceed to the traditional process of titanium nitride (TiN) hardmask, via photoresist buildup; then continue via lithography , and then go to etching. When we etch in one direction, it masks the TiN that defines the trench. Our newly developed material has a high selection for etching. This means that the via is perfectly etched into a rectangle that defines where the two metal layers cross each other. This technique eliminates EPE by maximizing via size and also eliminates the problems associated with interconnect size reduction.
Figure 5: Video showing through-hole flow combined with Applied’s material engineering capabilities to reduce mask count and improve EPE.
If a designer’s via layout is higher than the minimum resolution of lithography, they must use a multiple lithography-etch through-hole process. Using our new process, customers can define a larger via and create vias only at the intersection between two metal layers. This allows us to perfectly align the bottom and top device layers, saving process steps and enabling low impedance vias with wide process latitude (see Figure 6).
Dan Hutcheson, chairman and CEO of VLSIresearch, said: “The real innovation is that Applied Materials is able to build a new through-hole process that reduces EPE compared to the traditional multi-pattern imaging multi-image composite dicing mask approach. resulting in yield loss and lower cost, while also saving 0.7nm from a single via. In addition to improving yield, reducing EPE also increases revenue per wafer due to improved chip reliability and performance, chip It consumes less power.”
Figure 6: Fully selective self-aligned processing reduces resistance, increases yield, and reduces mask count compared to conventional processes
All in all, this “new strategy” brings us new tools to accelerate the progress of the industry roadmap, including addressing the size reduction challenge from a global perspective, in order to simultaneously address the various problems of PPACt. By co-optimizing Applied’s broad range of technologies, we can deliver new materials to enable new pattern size reductions, allowing cost-effective scaling to continue without compromising design. Welcome to the era of materialized graphic imaging!
About the Author:
Regina Freed is Global Executive Director of Graphics Imaging Technologies at Applied Materials. She has over 20 years of experience in the semiconductor industry and is responsible for R&D of logic/memory device lithography, measurement and defect inspection processes.