New exploration of Pinjie SiC driver design: how to avoid accidental activation?

[Introduction]With the gradual maturity of the SiC process and the continuous reduction in cost, SiC MOSFETs are gradually gaining popularity due to their overall performance superior to silicon-based devices by an order of magnitude, and are gaining more and more engineering applications. Compared with traditional Si power devices, SiC MOSFET has smaller on-resistance and faster switching speed, which greatly reduces system loss, improves efficiency, and reduces volume, thereby achieving high efficiency and high power density of the converter. Therefore, It is widely used in 5G data center communication power supply, new energy vehicle on-board charger, motor driver, industrial power supply, DC charging pile, photovoltaic, UPS and other energy conversion systems.

However, this fast transient process will make the switching performance of SiC MOSFET more sensitive to the parasitic parameters of the loop, and the requirements for driving design are more stringent. Taking discrete SiC MOSFET as an example, its dv/dt can usually reach 10~60V/ns depending on the current. The high-speed changing dv/dt in the power loop is coupled to the drive loop through parasitic capacitance, which will cause the gate to oscillate or even turn on by mistake, resulting in the bridge arm passing through and the device being damaged. Therefore, taking Pinejie 650V 40mΩ SiC MOSFET P3M06040K4 as an example, the phenomenon of SiC MOSFET driver false turn-on is deeply discussed, and a solution to avoid false turn-on is proposed.

01SiC MOSFET bridge arm crosstalk problem

As shown in Figure 1, the half-bridge application circuit of SiC MOSFET is shown. The turn-on process of the upper tube QH will generate a high-speed dv/dt change at the midpoint of the bridge arm, and the change of the lower tube Vds voltage will generate a displacement current through the Miller capacitor CGD. Positive voltage interference is generated on the pole drive resistance and parasitic inductance. When the voltage interference causes the gate voltage to exceed the threshold voltage of the device, it may cause the originally turned off lower tube to be turned on by mistake. For the convenience of analysis, the influence of parasitic inductance is temporarily ignored. From this, it can be obtained that the gate voltage of the lower tube during the turn-on process of the upper tube is:

New exploration of Pinjie SiC driver design: how to avoid accidental activation?

Where RG=Rg_ext+Rg_int , Vee is the turn-off voltage, when dvds/dt tends to infinity, the gate voltage limit is:

New exploration of Pinjie SiC driver design: how to avoid accidental activation?

Therefore, the methods of suppressing voltage crosstalk are: (1) Reduce gate drive resistance RG or gate parasitic inductance Lg (2) Active Miller clamp (3) Negative voltage turn-off (4) Increase gate-source capacitance CGS or Reduce Miller capacitance CGD

New exploration of Pinjie SiC driver design: how to avoid accidental activation?

Figure 1 SiC MOSFET bridge arm crosstalk problem

02Crosstalk suppression strategy

(1) Reducing the gate drive resistance is usually limited by the stress level of the device and the dv/dt speed. Too small drive resistance makes the dv/dt too large, which will aggravate the displacement current introduced by the Miller capacitor, which may also cause the gate voltage spike not to decrease. The smaller it is, the larger it is, so it is necessary to select the driving resistance reasonably under the condition of satisfying the stress. Reducing the parasitic inductance of the driving loop requires optimizing the PCB layout to minimize the distance between the driving components and the SiC MOSFET.

(2) The active Miller clamp circuit is shown in Figure 2. For a device that is turned off, if the gate generates a positive voltage disturbance that exceeds the set threshold Vth(MC), the switch SMC is turned on, providing a low impedance for the displacement current. discharge loop, thereby suppressing turn-on crosstalk. However, the clamping loop still includes the internal resistance of the device and the parasitic inductance from the connection point to the MOSFET. When this part of the voltage drop is large, the effect of the active clamping will be weakened, and it is possible that the device may still be turned on by mistake. Therefore, only when the internal resistance of the SiC device is small, it can have a good suppression effect. The internal gate resistance of Pinjie 650V SiC MOSFET is only 1.13Ω, so the use of active clamp can play a good role in suppressing crosstalk.

New exploration of Pinjie SiC driver design: how to avoid accidental activation?

Figure 2 Active Miller Clamp

(3) As shown in Figure 3, the gate voltage waveform of the always-off lower tube QL during the turn-on and turn-off process of the upper tube QH is given. It can be seen that the effect of negative voltage turn-off is equivalent to moving the entire gate waveform downward. Vee , which makes the positive voltage peak far away from the device threshold voltage, thus avoiding the wrong turn-on of the lower tube when the upper tube is turned on, but at the same time, the negative voltage peak of the lower tube increases when the upper tube is turned off. The allowable negative pressure of SiC MOSFET usually does not exceed -8V, so it is necessary to choose a reasonable negative pressure for shutdown. For Pinejie’s SiC MOSFET, -3V is recommended for shutdown.

New exploration of Pinjie SiC driver design: how to avoid accidental activation?

New exploration of Pinjie SiC driver design: how to avoid accidental activation?

Figure 3 The gate waveform of the lower tube when the zero voltage and negative voltage are turned off

(4) Paralleling capacitors at both ends of GS to increase CGS can well suppress the effect of voltage crosstalk, but it will slow down the turn-on speed to a certain extent. More serious is that when the internal parasitic inductance of the parallel branch is large, it may cause Increase gate parasitic oscillation. Therefore, the most suitable method is to increase the gate-source capacitance CGS or reduce the Miller capacitance CGD at the device level. In order to illustrate the anti-interference ability of the device itself to prevent false turn-on, the gate voltage change caused when dvds/dt tends to infinity is taken as a comprehensive evaluation index, that is, ΔVgs=ΔVds*CGD/(CGD+CGS), the smaller the ΔVgs, means that the gate The risk of false activation is smaller, and the anti-interference ability is stronger. Taking Pinejie 650V SiC MOSFET P3M06040K4 as an example, when ΔVds=Vbus=400V, the performance comparison of Pinejie’s SiC MOSFET and ΔVgs of international competitors can be obtained. As shown in Figure 4, it can be seen that Pincher’s SiC MOSFET has a very small ΔVgs and lower risk of false gate turn-on.

New exploration of Pinjie SiC driver design: how to avoid accidental activation?

Fig. 4 Comparison of anti-interference ability indexes of SiC devices with false turn-on

Source: Three Generations of Semi-Alchemists

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